Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orche
Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the [[20,2,6]] C_4-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of 4.6^{+6.2}_{-2.6}\times10^{-5} per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of 2.8^{+1.0}_{-1.6}\times 10^{-4} per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between C_4-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925^{+0.068}_{-0.245}\%. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the 10^{-6}-10^{-8} logical-error regime targeted for early fault-tolerant computation. Together, these results establish C_4-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.